1. Field
Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same.
2. Description of the Related Art
A conventional memory, for example, a DRAM, may include one transistor and one capacitor. However, there are limitations to the scalability of a conventional memory, due to the capacitor, in particular, the size of the capacitor. As a result, memories including one transistor (1T) and no capacitor as a memory cell, referred to as “capacitor-less” memories, have been developed. A capacitor-less 1T DRAM, hereinafter referred to as a conventional capacitor-less DRAM, may include a body that is electrically floated.
Generally, a conventional capacitor-less memory utilizes a silicon-on-insulator (SOI) wafer and identifies data controlling the floating body voltage by accumulating a majority carrier (either holes or electrons) in the floating body or by emitting the majority carrier from the floating body. When the majority carrier is accumulated in the floating body, this state is generally represented by a data “1”. Conversely, when the majority carrier is evacuated from the floating body, this state is generally referred to as a data “0” state.
There are two types of operation for a conventional capacitor-less memory device. The first is using the characteristics of MOS operation and the second is using the characteristics of BJT operation. In general, using the characteristics of BJT operation has been introduced and may have higher speed and/or better retention properties than MOS operation.